////`default_nettype none   
//synthesis translate_off 
`include "../../timescale.v"  
//synthesis translate_on
`include "../../DSP_define.v"
module Fet_Pkt_buffer(
                      sys_clk,
                      rst_n,
                      FP_en,                      
                      Fet_Pkt_i,
                      Fet_Pkt_rdy,
                      //stall,
                      Fet_Pkt_o
                      );                                                                                  
input                 sys_clk;
input                 rst_n;
input                 FP_en;
input[31:0]           Fet_Pkt_i;
input                 Fet_Pkt_rdy;
output[31:0]          Fet_Pkt_o; 

reg[31:0]             Fet_Pkt_o;

always@(*)
if(~rst_n)
  Fet_Pkt_o = 32'b0;
else if( FP_en)
  Fet_Pkt_o = Fet_Pkt_i;
else
  Fet_Pkt_o = Fet_Pkt_o;

endmodule
